Quad 2-line to 1-line Data Selectors/multiplexers. This X24C02 device has been acquired by IC Microsystems Sdn Bhd from Xicor, Inc. The X24C02 is. The LSTTL / MSI SN54 / 74LS is a high speed Quad 2-Input Multiplexer. Four bits of data from two sources can be selected using the common Select. S, 1 •, 16, Vcc. 1I0, 2, 15, E. 1I1, 3, 14, 4I0. 1Y, 4, 13, 4I1. 2I0, 5, 12, 4Y. 2I1, 6, 11, 3I0. 2Y, 7, 10, 3I1. GND, 8, 9, 3Y. Pin, Symbol, Description. 1, S, common data.
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The stitching of this circuit is given on figure 21, while figure 22 represents its logic diagram. Thus, one can compare numbers of 8, 12, 16 bits…. Form of the perso pages. In this chapter, we will examine logical circuits very much used to switch data: How to make a site? The number of the entries of order is a function of the number of ways of the multiplexer.
Let us examine simplest of the multiplexers, that with 2 ways. If a multiplexer has n input, it is said that it is about a multiplexer with n ways.
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The number of the inputs of a multiplexer defines the number of ways of a multiplexer. A binary comparator is a logical circuit which carries out the comparison between 2 generally noted binary numbers A and B. Using one or several entries of order, one switches one of the inputs towards the exit. The stitching and the logic diagram of this circuit are given on figure The first circuit compares the weak weights of A with the weak weight of B.
Figure 25 gives the diagram symbolic system and the mechanical equivalent of a multiplexer to 2 ways. For example for a multiplexer with 4 waysone needs 2 entries of order. A multiplexer can thus switch data made up of several bits. We will see how to produce using logical doors a comparator of 2 binary digits. That is translated in the table of figure When this entry is with state 1it is the data Bi which is transferred in Yi. The combinative network of figure 26 can provide the signal S.
This table, one can extract the equation from the exit S following: A multiplexer can be compared with a mechanical switch. Return to the synopsis. Forms maths Geometry Physics 1. Electronic forum and Infos.
Quad 2-line to 1-line data selectors / multiplexers 74157
High of page Preceding page Following page. According to the uc of the entry of selection Athe exit S recopy either the D0 entry, or the D1 entry.
That is to say to compare the two binary digits A and B. All these considerations are translated in the truth table of figure The integrated circuit is a comparator 4 bitsi.
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Its equation is thus A. By putting in series two comparatorsone can compare two numbers of 8 bits. Figure 29 represents the diagram symbolic system and the mechanical equivalent of a multiplexer with 4 ways.
The integrated circuit is a quadruple multiplexer with 2 ways at entry of common selection. Click here for the following lesson or in the synopsis envisaged to this end. To contact the author. Static page of welcome.
– Quad 2-input multiplexer – ChipDB
Electronic forum and Poem. These circuits have several inputs and only one exit.
We deduce the equation from it from S following: In general, the selected entry carries in index the state corresponding to the combination of the entries of order.